Design for Test (DFT) Analysis
As is the case with any test methodologies, board and system test based on JTAG/Boundary Scan requires some Design for Testability (DFT).
For example, all devices featuring a JTAG compliant Test Access Port (TAP) should be linked up
in one or more scan chains that are accessible, ideally through a connector.
Under certain circumstances it may be desirable to configure the Unit Under Test with multiple
scan chains, in other cases just one chain may be beneficial.
Certain types of Boundary Scan test applications demand their own set of DFT rules.
The point is, the board/system designer is in charge of making the Unit Under Test Boundary Scan testable.
It is highly recommended to involve test engineers in design reviews in order to ensure a
comprehensive test strategy can be implemented.
GOEPEL can provide Design for Testability guidelines and even offers DFT analysis for Boundary Scan free of charge.