Tutorials
JTAG / boundary-scan tutorial |
JTAG / boundary scan applications |
IEEE 1149.1 related standards
JTAG / boundary-scan tutorial
Hardly any other test procedure has changed the testing grounds for manufacturers of
electronic products the way In-Circuit Test did during the last 40 or so years.
The reason for this triumph was that in-circuit testing is not confined to the test
of the quality of the product but that it also shows the reasons for faults.
Thus, the manufacturer has a tool that allows the creation of an automated quality control
system. For example, if always the same faulty component were detected in a batch of boards,
it would be recommendable to change the supplier. On the other hand, if the main reason for
faulty boards is bad solder joints, the soldering process should be improved. Strictly speaking,
one might think that the “philosopher’s stone” of Test had been found.
This would be true – if it were not for the word "in-circuit". To test within a circuit is easier
said than done, and it has not been possible without using bed-of-nail fixture technology.
After some initial difficulties had been overcome, it was no problem to create the appropriate
bed-of-nail fixture for any circuit - at least until the mid 1980s.
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JTAG / boundary-scan applications
IEEE 1149.1 can be utilized for a variety of test, debug, and in-system programming applications.
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IEEE 1149.1 related standards
IEEE Std 1149.1 provides a foundation other standards have been building on and ongoing
standardization efforts continue to exploit and improve upon.
These standards include
IEEE Std 1149.4,
IEEE Std 1149.6,
IEEE Std 1149.7,
IEEE P1149.8.1,
IEEE Std 1450,
IEEE Std 1500,
IEEE Std 1532,
IEEE Std 1581,
IEEE P1686,
IEEE P1838, JEDEC standards, such as
JESD-71 / STAPL, and industry initiatives, such as SJTAG.
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