In-Circuit Test (ICT)
Hardly any other test procedure has changed the testing grounds for manufacturers of electronic products the way
In-Circuit Test (ICT) did during the last 40 or so years. The reason for this triumph was that in-circuit testing
is not confined to the test of the quality of the product but that it also shows the reasons for faults.
Thus, the manufacturer has a tool that allows the creation of an automated quality control system.
For example, if always the same faulty component were detected in a batch of boards, it would be recommendable
to change the supplier. On the other hand, if the main reason for faulty boards is bad solder joints, the
soldering process should be improved. Strictly speaking, one might think that the “philosopher’s stone” of test had been found.
This would be true – if it were not for the word "in-circuit". To test within a circuit is easier said than done,
and it has not been possible without using bed-of-nail fixture technology. After some initial difficulties had been overcome,
it was no problem to create the appropriate bed-of-nail fixture for any circuit - at least until the mid 1980s.
Soon, there were ideas about how the costs of test could be reduced by more universal approaches,
e.g. by using the same bed-of-nail adapter for different test units. However, the technology of the component
manufacturers rapidly developed, resulting in more and more gates placed onto the silicon die; nowadays entire
systems are implemented within one integrated circuit. These systems still have to communicate with the environment,
though, requiring the component to be equipped with pins. With drastically increased functional density of a circuit,
the number of its pins inevitably has to rise, too. Sometimes simple laws of geometry become evident: room to put all
necessary pins on the device package is getting scarce. The only way out is to reduce the space between the pins.
So-called "fine-pitch packages" with a space of 0.3 mm between the pins are the standard today; technologies such as
BGA (ball-grid-array) or those that completely dispense with the casing - such as COB (chip on board) – are used more and more.
However, these new package technologies and the connection density that comes with them cause trouble for bed-of-nail
fixture based testers. For if the raster of the connections gets narrower, then inevitably the probes of the bed-of-nails,
too, have to be placed closer to each other. Yet, there are physical limits to this. Although, a possible way out of the
dilemma, distributing test pads over the board is advantageous for the adaptation, it works against the purpose of saving
space through highest integration. Here the idea of Boundary Scan comes in.
Boundary Scan basically means to "get rid of
the external test probe" (figure on the right). Boundary Scan is replacing the external probes of a test fixture with device-internal ones,
the so-called "Electronic nails", being installed at the periphery of the functional silicon (on the device boundary).
Learn more about JTAG / boundary scan ...
A combination of in-circuit test and JTAG / boundary scan is beneficial whenever mechanical access with a bed-of-nail fixture is
difficult or when fixtures get very expensive because of their complexity. Such integrations make sense even if there may be a small
number of JTAG / boundary scan-capable components on the PCBA (printed circuit board assembly).
Advantages of combining ICT and boundary scan:
- Fast test execution
- Very high fault coverage even for highly complex and densely packed PCBAs
- Reduction of bed-of-nail fixture cost
- Simple test program generation
Learn more combining JTAG / boundary scan and in-circuit test ...