IC (chip) level test solutions and services
JTAG validation and BSDL verification
In order to enable their customers to reap the benefits of JTAG / boundary scan, IC designers and vendors want to ensure that their devices are compliant with the respective IEEE standards, such as IEEE Std 1149.1 and IEEE Std 1149.6, for example.
Board and system designers and test engineers wanting to take advantage of the benefits of JTAG, for example for connectivity tests, rely on a standard conform implementation of test resources (such as a boundary scan register with EXTEST functionality) as well as a correct description of JTAG / boundary scan features implemented in a particular integrated circuit in form of a boundary scan description language (BSDL) file.
Test generation tools use these BSDL files in conjunction with board and system level netlist information to get an understanding of the unit under test and to automatically generate boundary-scan test programs.
GOEPEL Electronics offers an innovative tool suite for automated generation of simulation vectors and test patterns for chip-level validation and verification of IEEE 1149.1 and IEEE 1149.6 compliant implementation.
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Chip-embedded instrumentation
Many of today's complex integrated circuits include chip-embedded instrumentation that device designers utilize for design validation and wafer test. However, these instruments are rarely made available for use during board and system level test, once the device is mounted on a printed circuit board. Some of these instruments, however, would be very useful for board and system level tests (built-in self tests [BIST] and temperature and voltage monitoring are just a few examples).
The industry has recognized this as an important issue. An IEEE working group has formed to create a new standard, IEEE 1687, to address the access to such chip-embedded instruments and the documentation of the access to and the control of these instruments.
In 2010, GOEPEL Electronics has introduced a software technology called ChipVORX as part of our JTAG / boundary scan tool suite SYSTEM CASCON. Paving the way for IEEE 1687 support in our JTAG / boundary scan software and hardware systems, ChipVORX enables the control of on-chip intellectual property (IP) of any kind, including IP for test, validation, and in-system programming.