IEEE Std 1149.1 - the JTAG / boundary-scan architecture
The fundamental components of the boundary scan architecture are the TAP (Test Access Port) and the boundary scan
register made up of boundary scan cells.
The TAP controller is constructed as a finite state machine with 16 states. The transition from one state
to another always occurs with the rising edge of TCK, with the level on TMS selecting the next state.
The whole Boundary Scan structure must be implemented as synchronous design according to the standard.
After power on of the device or after the TAP is forced into the reset state the Boundary Scan structure is inactive.
Besides the Boundary Scan Register (BSR) an IEEE 1149.1 compliant device also contains an Instruction Register (IR)
and a Bypass Register (BPR). The IR is used to define the test mode (e.g. Sample, Extest, Bypass, etc.).
The purpose of the BPR is to shorten the scan chain. Other optional data registers may be implemented,
such as an Identification Register.
To distinguish whether data or an instruction is shifted, the TAP state machine has two separate paths featuring
similar states (e.g. Scan DR / Scan IR). The states most essential for the test operation are the shifting of
test data (Shift DR), the capturing of data into the register (Capture DR), the delivery of the test data to the
output latches of the scan cells (Update DR) as well as the analogous states for the instruction register
(Shift IR, Capture IR, Update IR).
As can be seen in the state diagram on the right, the transition from one state to another depends on the logic value on TMS.
TMS (Test Mode Select) is one of the four signals that are also referred to as the Test Bus, or TAP interface, or JTAG pins.
The TAP (Test Access Port) is a state machine synchronized by the Test Clock (TCK). The two other mandatory signals of the
Test Bus are used for the test data transmission: Test Data In (TDI) and Test Data Out (TDO). /TRST (Test Reset, low active)
is the only optional signal defined for the IEEE 1149.1 compliant Test Bus.
Beside the Boundary Scan Register (BSR), the standard specifies the existence of at least a Bypass Register (BPR) as
additional data register. The BPR bypasses the BSR and thus shortens the scan chain by providing a 1 cell connection
between TDI and TDO of the device. The data register between TDI and TDO of a device is selected by the instruction
previously scanned into the Instruction Register.
Basic functions of the Boundary Scan architecture
- Parallel capture of test result vectors into the Boundary Scan cells (capture)
- Serial shifting in of test vectors and simultaneous shifting out of captured test results (shift)
- Parallel connection of loaded test vectors to the circuit node that has to be tested (update)
- Test / stimulation of the internal connections of an integrated circuit (internal test)
- Test / stimulation of pin connections on a board- or system-level circuit (external test)
To learn more about IEEE Std 1149.1, including different types of boundary scan cells, instructions, and the utilization of these test resources, please download a tutorial.
Send an inquiry via email
IEEE Std 1149.1 working group website