IEEE P1838
The IEEE P1838 working group is proposing the standardization of die-level features, that,
when compliant dies are brought together in a stack, comprise a stack-level architecture that
enables transportation of control and data signals for the test of intra-die circuitry and
inter-die interconnects in a multi-die stack. These test features would be usable in both
pre-stacking and post-stacking situations.
The primary focus of inter-die interconnect technology to be addressed by IEEE P1838 is Through-Silicon Vias (TSVs).
However, this does not preclude its use with other interconnect technologies such as wire-bonding.
The IEEE P1838 standard will include a 3D test wrapper hardware with features that enable transportation of test signals
as well as a description language for these test wrapper features. IEEE P1838 will likely be based on
scan-based test access and may leverage existing test access ports (e.g. IEEE Std 1149.x), on-chip DFT features
(e.g. IEEE Std 1500, IEEE P1687.
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ITC 2010 poster discussing 3D IC Test IEEE P1838 working group website |