JTAG / boundary scan tools by GOEPEL electronics

Questions to consider when choosing a JTAG / boundary scan system

Do you have a CPU, CPLD, FPGA, or other complex devices and/or components in high density packages such as BGA, microBGA on your board?

What type of non-boundary scan devices does the Unit Under Test (UUT) feature (e.g. Static Memory [SRAM], Dynamic Memory [SDRAM, DDR SDRAM, ...], NOR Flash, NAND Flash, serial EEPROM, discrete logic devices [e.g. 74LVT00] or Decoders, peripheral connectors with many digital signals, and/or DIMM sockets)?

When/where in the UUT's product life cycle do you intend to use JTAG/boundary scan?

For what purpose do you intend to implement this JTAG / boundary scan system: Design Validation and Prototype Verification, Manufacturing Test, Repair and Troubleshooting, Field Service, or for some other purpose?

Do you intend to develop your own JTAG/boundary scan applications, or would you outsource the test development?

Would this station be intended for boundary scan test only or would you want to test your products and also program CPLD or Flash devices or serial EEPROMs?

What are the primary types of JTAG / boundary scan applications you are interested in? For example: Connectivity Tests (finding manufacturing faults, such as opens, shorts, stuck-at faults), In-System Programming for CPLD / FPGA devices, In-System Programming for serial EEPROM and/or Flash devices, In-System programming of On-Chip Memory (e.g. Flash memory inside a CPU, DSP, or Micro-Controller), Utilize On-Chip Emulation for structural tests and for JTAG controlled functional tests, some other application?

What should this software package allow me to do? For example: Develop JTAG / boundary scan applications, Generate tests automatically, Write tests manually in a scripting language, Execute test and In-System Programming routines, Generate detailed pin and net level diagnostic messages in case of detected defects, Debug JTAG / boundary scan applications, Present the Layout and/or Schematic view of the Unit Under Test.

Would you prefer a node-locked license (USB dongle) or a floating (network) license? In case of a network license, would you want to share the license with other facilities in the country or even globally?

How would you like to connect the JTAG / boundary scan controller hardware to the tester PC: USB, PCI, PXI, Ethernet, PCI Express, PXI Express, LXI, Cabled PCI Express, some other bus?

Do you intend to test/program multiple UUTs at the same time (concurrently) with this test system?

What is the maximum TCK frequency the boundary scan devices on your UUTs typically support?

Would this station be intended for boundary scan test only or would you also want to program Flash devices or serial EEPROMs?

Have you experienced or expect to experience any Design for Test (DFT) issues related to JTAG / boundary scan, such as a Scan Chain that is not designed properly, TAP signals on JTAG compliant devices that are only accessible through test points, Compliance Enable conditions that can only be satisfied by probing test points, or some other DFT problems?

Do you need tester I/O channels in order to include peripheral I/O connectors on the UUT in the boundary scan tests?

Do you intend to run the JTAG/boundary scan system as a stand-alone installation or would you want to integrate the tools in third-party ATE equipment (such as In-Circuit Tester, Flying-Probe Tester, Functional Tester)?

Are you interested in a DFT Analysis on one of your UUTs? Will you require system and/or test technology training?

Are you interested in our test development services, BSDL Verification Services, and/or turn-key solutions?

For details or to request a quote, please contact us.