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Market segments Aerospace Automotive Consumer Electronics Contract Manufacturers Industrial Controls Healthcare Electronics Defense Electronics Telecom, Networking Applications IC / device test JTAG validation and BSDL verification Chip-embedded instrumentation PCBA / sub assembly test Prototype verification Structural manufacturing test Automated optical inspection Automated X-ray inspection Conformal Coat Inspection Field service JTAG / boundary scan Processor emulation test In-system programming Serial EEPROM Flash EEPROM CPLD and FPGA System level test Functional test Brands ADYCS CASCON GALAXY CASCON POLARIS CASLAN Chameleon ChipVORX CION FastScale HyScan JULIET OptiCon SCANASSIST SCANBOOSTER SCANFLEX SCANVISION SYSTEM CASCON TAPChecker TOM VarioCORE VarioTAP Virtual Scan Pin Products Automated Optical Inspection systems Automated X-Ray Inspection systems Automotive Test Solutions Chip-embedded instrumentation tools EDA software In-system programming tools JTAG / boundary scan software CASCON GALAXY CASCON POLARIS SCANASSIST SCANVISION JTAG / boundary scan hardware CION PicoTAP SCANBOOSTER SCANFLEX Other JTAG accessories JTAG software and hardware bundle SCANBOOSTER Designer Studio ATE Integration packages JULIET Tester Processor Emulation Test tools General purpose test modules I/O modules Interface modules Power modules Simulation modules Switching modules Turn-key JTAG / boundary scan tester Support Contact Technical Support Contact Sales Support Services BSDL Verification DFT Analysis Technical Support Test Development Services Training GOEPEL GENESIS Event registration e-Bulletin signup Education DFT Guide (blog) GOEPEL Electronics' Blog Downloads DFT Guidelines BSDL SyntaxChecker Tutorials, webinar transcripts and recordings Product information Test technology and standards IEEE 1149.1 IEEE 1149.4 IEEE 1149.6 IEEE 1149.7 IEEE P1149.8.1 IEEE 1450.x IEEE 1500 IEEE 1532 IEEE 1581 IEEE P1687 IEEE P1838 JESD-71 / STAPL SVF In-Circuit Test Flying Probe Test JTAG / boundary scan Other technologies Glossary Upcoming events Webinars Trade shows Seminars Training News News releases Sign up for e-Bulletin Upcoming Events Corporate information About us Survey Contact us Partners Privacy Policy Sitemap

JULIET benchtop tester

Typical design for test (DFT) problems, such as:

• TAP signals not being accessible via an edge connector,
• Compliance Enable pins only being accessible via test points,
• Handling being inefficient (too many cables to handle),
• Boundary-scan test coverage lacking (improvements possible through test points of connector pins if accessible with Tester I/O), or
• Overall test coverage missing analog circuitry,

can be overcome with an integrated JTAG/Boundary Scan Tester in a desktop system, suitable for prototyping and production.
The JULIET system provides integrated system electronics and an exchangeable UUT adaptor and is controlled by external PC or laptop via a USB 2.0 or LAN interface. JULIET supports the execution of JTAG / boundary-scan tests, in-system programming of Flash, CPLDs and MCUs, and processor controlled tests (VarioTAP).

Download a poster providing mode details about the JULIET system.

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