TAP Checker

The innovative TAP Checker tool suite enables automated generation of simulation vectors and test patterns for chip-level validation and verification of IEEE 1149.1 and IEEE 1149.6 compliant implementation.

Verify your JTAG / boundary scan designs before committing them to mass production
Keep your customers happy by supporting their test engineering groups with IEEE 1149.x compliant JTAG / boundary scan implementations
Save time, money, and nerves when validating, debugging, and verifying you JTAG / boundary scan implementations
Support failure analysis efforts by verifying the correctness and standard compliance of your JTAG / boundary scan implementations

TAP Checker is based on a modular platform architecture with a central database and individually licensed modules for data import, automated test vector generation, and data export. The tool supports single chips as well as multi-chip modules and 3-D silicon devices.

After importing the BSDL file - a process which includes syntax, semantics, and consistency verification - the user has access to a multitude of parameterized options, providing the means to generate optimized testbenches.

Automated generation of test bench for validation and verification of JTAG / boundary scan designs
Tool flow includes BSDL verification (syntax and semantics)
Supporting IEEE 1149.1 and IEEE 1149.6
Support for multi-chip modules and 3-D silicon devices
Output formats: Verilog (IEEE 1364), VHDL (IEEE 1076), and STIL (IEEE 1450)
For Sun Solaris, Linux, and Windows
GUI and command line interface

Learn more about TAP Checker on www.goepel.com.

Please contact us for more information or for a software demo.