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BSDL TestWriter™

The BSDL Testwriter™ software is a tool for the automated generation of a test bench for Boundary Scan designs, supporting IEEE 11491. and IEEE 1149.6. It processes BSDL files as input and generates vectors for functional verification of all Boundary Scan structures. Automating the verification process, manual errors are avoided and the test efficiency is substantially improved. The BSDL Testwriter can optionally generate a STIL (IEEE Std 1450) output. This link allows the use of the generated vectors for a production test of the physical IC on automated test equipment (ATE).

BSDL TestWriter accepts a BSDL file and optional user defined package file(s) as input and verifies the syntax and semantics of the file. If syntax and semantics are compliant to IEEE 1149.1 and possibly IEEE 1149.6, BSDL TestWriter can generate Verilog Test Bench, for example, and/or STIL files or other tester specific test programs.


The verification of Boundary Scan structures for IEEE 1149.1 (and possibly IEEE 1149.6) compatibility and design specifications is very time consuming and costly without automated tools. Using the BSDL Testwriter, IC design engineers can minimize the number of verification iterations by simulating the generated test bench. Furthermore, human errors are avoided and the overall efficiency of the verification process is substantially improved. With the STIL output, for instance, the BSDL Testwriter™ can also be used in IC production test. The generated test patterns can be linked to a respective IC tester and can be used for the verification of the physical chip. The quality of the generated test bench ensures highest fault coverage.

The generated Verilog or VDHL test bench allows the application of the vectors on a wide variety of simulators. To support the workstation environments typically used for ASIC / ASSP design, the BSDL Testwriter™ is available for Sun SOLARIS 2.6+ and MS Windows operating systems.

BSDL TestWriter features

  • BSDL syntax and semantics check;
  • Compliant to IEEE 1149.1 (1990, 1994, 2001) and IEEE1149.6 (2003);
  • Automated Test Bench generation with various standardized and tester specific formats;
  • Verilog output for use in simulators;
  • STIL (IEEE Std.1450) or tester specific output for IC test equipment;
  • Includes support for asymmetric ports (pull-up / pull-down) and differential ports;
  • Control from command line or GUI;
  • Available for Sun Solaris 2.6 or higher, as well as Microsoft Windows NT / 2000 / XP

Tests generated by BSDL TestWriter

(depending on the JTAG/Boundary Scan features documented in the BSDL file)
  • BYPASS Test,
  • IDCODE Test,
  • RESET Test,
  • TAP States Test,
  • Update Latch Timing Test,
  • Control Cell Uniqueness Test,
  • ID Register Connection Test,
  • HIGHZ Test,
  • CLAMP Test,
  • User Defined Instruction Test,
  • Pinmapping Test (Inputs Test, Outputs Test, including DC parametric test),
  • Boundary Scan Cell Capture Test for Intest and Extest;

Output formats supported by BSDL TestWriter

  • Verilog,
  • VHDL,
  • STIL,
  • WGL,
  • Agilent 93K,
  • Agilent 3070 (VCL),
  • Teradyne,
  • TI TDL;















































For detailed information about the BSDL TestWriter please contact us.

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