Applications

Typical applications for CASCON GALAXY include, but are not limited to, test and in-system programming applications at device, board, and system level, such as the following:

• BSDL verification and validation;
• Prototype verification;
• Production test;
• Field service;
• Scan path validation;
• Connectivity Test: detection and localization of opens, shorts, stuck-at-0/1 faults;
• Analog and mixed-signal measurements;
• Digital pattern capturing, pattern generation;
• Interface testing;
• Debugging and repair support for boards/systems that don't boot up in functional test;
• Basic functional test;
• Built-In Self Test (BIST) execution;
• In-System Programming of FLASH; 
• In-System Programming of serial EEPROM;
• In-System Programming of PLD/FPGA;
• Integration with In-Circuit Test to reduce cost of test, improve test coverage;
• Integration with Flying Probe Test to reduce test time, improve test coverage;
• Integration with Funtional Test to reduce cost of test, improve diagnostics, test access;
• Embedded Boundary Scan test and ISP;

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Screenshots

CAD Import	Automated test program generation (ATPG) and Automated FLASH program generation (AFPG) in SYSTEM CASCON are based on the UUT's net list and device model information. The net list of the UUT is imported with the CAD Import process. SYSTEM CASCON supports more than 50 CAD formats, and formats not supported out-of-the-box can be handled with customized PERL scripts. Graphical Schematic and Layout data can be imported using SCAN VISION import processes, which are optionally available for SYSTEM CASCON. The output of the CAD Import process is a Component and Netlist file in a proprietary format, used as input for optional net merging processes and for the Component Explorer.
Device libary	SYSTEM CASCON uses device libraries to store information about Boundary Scan and non-Boundary Scan components. This information is used by the Parsing process to analyze the board structure and create a UUT description that promotes safe test pattern [i.e. automatically generated test pattern does that does not create any bus contentions or other problematic or potentially destructive conditions on the Unit Under Test]. The software is delivered with a system library. Users typically create project libraries to which they add device models (either by copying from the system library, or by importing device description files in BSDL, BSDM, or IBIS format, or by creating a new device model in the library). The SYSTEM CASCON Device Library includes import processes for BSDL (Boundary Scan Description Language, standardized in IEEE 1149.1), BSDM (a proprietary device description language for non-Boundary Scan devices), and IBIS (an industry standard format for device descriptions, providing primarily information about pin out and pin functionality). All these import processes include syntax and semantics checks. Device models in a CASCON library can also be exported as BSDL or BSDM file, and can be copied between libraries.
Net List Merger	The Net List Merger can be used to merge multiple net lists to obtain a system net list, which is used to generate test programs for a specific system configuration. Furthermore, nets within the same net list file can be merged with this tool, accommodating test programs incorporating loopback connectors. For the merging process, the user selects the net list file(s) to be merged and defines the connections (e.g. "merge all pins on these two devices ...", or "merge this net with this net ...", or "merge all nets from these two files that have identical names ...", etc.). Multiple merging steps can be created to accommodate various system configurations. The resulting DIF file (or Parser file) is analyzed with the Component Explorer or used directly by a Parsing process. The net merging tool allows a user to easily create test applications for system configurations. Such system configurations could consist or a mother board that carries one or more daughter cards, or a backplane based system with one or multiple cards plugged into backplane slots, supporting interconnect tests between those daughter cards or between  plug-in cards in various system slots. Note: System Level test demands respective Design for Testability considerations. See our DFT blog or download a DFT booklet.
Component Explorer	The Component Explorer is used to assign device models to Boundary Scan and non-Boundary Scan devices and to classify passive components such as resistors, connectors, capacitors, etc. The easy to use graphical user interface simplifies this important step. The assignments made in the Component Explorer are used by the Parsing process to analyze the board structure and to create a UUT database file that promotes safe test pattern [i.e. automatically generated test pattern does that does not create any bus contentions or other problematic or potentially destructive conditions on the Unit Under Test].
Create New Executables	After the Parsing process and the compilation of the Boundary Scan chain description, the software recommends test applications suitable for this specific Unit Under Test. The user can accept the recommendations or add or remove test and In-System Programming (ISP) applications. Once confirmed, the framework for the selected applications is created by the software and the individual test and ISP applications can be generated and compiled.
Automated Test Program Generation for Infrastructure Test	In CASCON GALAXY, the Infrastructure Test, which verifies the scan chain integrity, is generated automatically by a respective Automated Test Program Generator (ATPG) tool. The resulting test program is written in CASLAN (SYSTEM CASCON's  Boundary Scan programming language) and can be compiled into CASCON Object Code (*.CAC), Standard Test Aand Programming Language (STAPL, Jedec Standard 71), or Serial Vector Format (SVF). The Infrastructure Test verifies the existance, length, and capture values of the IDCODE and possibly USERCODE register, the Bypass register, the Instruction register, as well as the existance and length of the Boundary Scan Register for all devices in the scan chain. The test can detect and diagnose scan chain errors. Scan Router devices are handled automatically.
Automated Test Program Generation for Interconnect Test	The Interconnect Test checks the Unit Under Test for structural faults on I/O pins introduced during the manufacturing process, such as open pins, stuck-at-1/0 pins, and shorted nets. This test includes not only Boundary Scan I/O pins, but also transparent components between two Boundary Scan pins, such as serial resistors and buffers/transceivers. Even pull-up and pull-down resistors can be checked for presence in many cases. The Interconnect Test is generated automatically by a respective AutomatedTest Program Generator (ATPG) tool. The resulting test program is written in CASLAN (SYSTEM CASCON's  Boundary Scan programming language) and can be compiled into CASCON Object Code (*.CAC), Standard Test Aand Programming Language (STAPL, Jedec Standard 71), or Serial Vector Format (SVF). The Interconnect Test in SYSTEM CASCON supports both IEEE 1149.1 and IEEE 1149.6 compliant devices. Scan Router devices are handled automatically.
Automated Test Program Generation for Memory Cluster Test	The Memory Cluster Test verifies connections between a Boundary Scan device and a memory device (such as an SRAM, DRAM, SDRAM, DDR SDRAM, etc.), including buffers or glue logic embedded between the two. Even though the Interconnect Test typically already tests the address, data, and control bus for shorts, the memory cluster tests includes a open faults on the memory device. This test is generated automatically by a respective AutomatedTest Program Generator (ATPG) tool. The test is based on functional access cycles to the memory, applied through Boundary Scan I/O pins. The functional access cycles are part of the memory device models in the CASCON Device Library.. The resulting test program is written in CASLAN (SYSTEM CASCON's  Boundary Scan programming language) and can be compiled into CASCON Object Code (*.CAC), Standard Test Aand Programming Language (STAPL, Jedec Standard 71), or Serial Vector Format (SVF). Just like in any other application in SYSTEM CASCON, Scan Router devices are handled automatically.
Automated Test Program Generation for Logic Cluster Test	Based on a Cluster Table describing the actual test pattern, the Logic Cluster Test verifies the basic functionality of a logic cluster or other non-Boundary Scan circuitry that can be stimulated and observed with Boundary Scan I/O pins. The Logic Cluster Test is generated automatically by a respective AutomatedTest Program Generator (ATPG) tool.  The resulting test program is written in CASLAN (SYSTEM CASCON's  Boundary Scan programming language) and can be compiled into CASCON Object Code (*.CAC), Standard Test Aand Programming Language (STAPL, Jedec Standard 71), or Serial Vector Format (SVF). Scan Router devices are handled automatically.
Automated FLASH Program Generation	FLASH programming applications, similar to Memory Cluster Test applications, are based on a functional description of access cycles (such as read ID, erase, program, read, etc.) provided in a FLASH device model. The actual FLASH programming application is generated automatically, whereby the Boundary Scan resources accessing the FLASH are assigned automatically. The user has the option to modify FLASH access, for example to control one or more of the control signals from a Parallel I/O Pin in order to dramatically improve programming speed. Furthermore, the user selects the actual actions to be executed. Optionally, these actions can even be presented in a dialog box at run-time to allow the operator to selectively run certain tasks. The progranming data can be provided in Intel HEX files, Motorola S-Record files, and in binary image files, while the actual programming file can be fixed as part of the programming routine, or it can be selected by the operator at run-time. Just like for any test application in SYSTEM CASCON, Scan Router devices are handled automatically.
ISP for PLD and FPGA	In-System Programming of PLD and FPGA devices is supported through STAPL, JAM, and SVF files. Furthermore, SYSTEM CASCON supports IEEE 1532, including concurrent programming.   Scan Router devices are handled automatically.
Net Browsing	The Net Browsing tools in SYSTEM CASCON (NetList Navigator, NetList Explorer) provide quick and easy access to all nets on the Unit Under Test as well as to all pins connected to these nets and their properties. Color coding allows quick visual differentiation between nets of certain types, such as test bus nets vs. Boundary Scan nets vs. Power and Ground nets, and so on.
Test and ISP execution	The test and in-system programming applications can be executed individually or as part of a batch sequence. Such applications can be run once or continuously. Test results are presented on screen and are also written into a test result file. In case of faults, automatically generated test programs provide detailed diagnostic messages in plain English (unless they are executed in Go/No-Go mode). In SYSTEM CASCON, any test or ISP application checks the scan chain integrity everytime test or programming data is shifted through the chain, therefore ensuring that a broken scan chain does not cause pseudo error messages or unecessarily long execution times. If necessary, this feature can be turned off at any time in a test or ISP application. The test result file can contain additional information, such as date and time stamps, the UUT serial number, and additional comments. Multiple UUTs of the same type can be tested and programmed in parallel in order to increase throughput. .
Multi Mode Debugger	CASCON GALAXY includes a powerful multi-mode debugger. This debugger provides various ways to observe any Boundary Scan resources on the UUT and to interact with the test application, even to modify existing or to add additional test steps. One of the step modes even allows the user to inspect the scan pattern at the lowest level, where the debugger presents the pattern on the TMS, TDO, and TDI, which can also be stored in a file for later reference.
Advanced Vector Browser	For Go/No-Go test applications generated automatically, or for manually written tests, or even for tests that include diagnostic messages, the Advanced Vector Browser provides an inside look at the actual test pattern applied to the Unit Under Test. Mismatches between expected and measured pattern are highlighted in red.
Test Coverage Analyser	The Test Coverage Analyser generates an overall test coverage report based on the actual test programs. It considers ALL nets on the Unit Under Test and provides details about tested and not tested (or not fully tested) pins and nets. The file contains lists detailing pin and net oriented test coverage and provides statistics at pin, device, and net level. The contents of the Test Coverage Report file can be customized. It can be generated for an individual test or for a batch of test programs.
Project Archiving	Once test development is finished (or even in between, for back-up or for support purposes) the project files can be archived. The contents of the archive can be customized. Date and time stemps can be applied in order to ensure data consitency. The archive also includes data compression. A project archive can be unpacked at another station. This station then will provide the same test and ISP applications and settings for this UUT as the station the project archive has been created on. The same way, modifications to a project or to a specific test application can be transferred to other stations as well.
Scan Vision	The Scan Vision tool links into the UUT database in SYSTEM CASCON and presents the layout and/or schematic. Pin and net level faults can be presented in Scan Vision, allowing the operator to quickly identify the components involved and assisting in fault isolation. During test development, Scan Vision can be useful in identifying/locating specific devices, pins, or nets; in graphically reviewing the test coverage on the UUT; on by visually presenting different types of devices, pins, and nets in different colors, for example. Scan Vision provides cross referencing with the Net Browser tools and can be accessed from all development tools, the multi-mode debugger, and the test execution environment. It is even accessible from the CASCON API.
Batch editor	The batch editor can be used to interactively create batch sequences, combining multiple test and ISP applications. A batch file can contain branches and loops, and even calls to external programs. Batch sequences are not compiled and can therefore be modified at any time.
CASCON Online Help	SYSTEM CASCON includes an extensive online help.
CASCON Navigator	Not as detailed and in-depth as the CASCON online help, the CASCON Navigator provides a quick overview of the Boundary Scan technology and of the test and ISP development flow in SYSTEM CASCON. It supports novice users in quickly gaining experience with the software and helps infrequent users to recall the individual test development steps. Even though SYSTEM CASCON provides and intuitive user interface and guides the user through the individual development steps, the CASCON Navigator can provide helpful tips and background information.

Licensing

• Node-locked licensing, based on dongles/hardkeys by ALADDIN, and
• floating licensing, based on flexLM by Macrovision;

The node-locked licensing scheme required a LiMaS Parallel Port or USB (default) dongle to be connected to the host machine (typically a PC). The dongle contains a system ID and can be programmed with software enable codes. Upgrading a node-locked software simple requires a reprogramming of the dongle (at customer's site, no shipping of new dongles required). The SYSTEM CASCON software works only on the host machine that has the dongle connected to it. Sharing a license in a company would require the dongle to be moved from one machine to another machine. Each purchased software package is delivered with a dedicated dongle. Sharing licenses is supported in a floating license environment.

SYSTEM CASCON also offers a network (or floating) licensing scheme. The floating license is based on Macrovision's flexLM tool. The flexLM lisence server software is installed on a machine accessible from the client machines which are supposed to run the CASCON software. The number and the type of available CASCON software licenses is documented in a license file, which is used by the flexLM server in conjunction with the GOEPEL client for flexLM to manage the CASCON licenses. The CASCON software can be installed on any PC in the network (even in remote locations). When CASCON is started and running, such a client machine accesses the license server in order to obtain a software license.
The floating license scheme used in SYSTEM CASCON allows for tool licensing, dynamic license requests, and – obviously – multi-seat configurations. This combination of licensing features provides for the best possible tool utilization. If multiple users need to work with SYSTEM CASCON, a floating license arrangement provides the best value.

For detailed information about CASCON GALAXY please contact us.

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