Design for Testability
Board and system test based on JTAG/Boundary Scan requires some Design for Testability (DFT). For example, all devices featuring a JTAG compliant Test Access Port (TAP) should be linked up in one or more Boundary Scan chains that are accessible, ideally from a board edge connector. Under certain circumstances it may be desirable to configure the Unit Under Test with multiple Boundary Scan chains, in other cases just one chain may be beneficial. Certain types of Boundary Scan test applications demand their own set of DFT rules. The point is, the board/system designer is in charge of making the Unit Under Test Boundary Scan testable. It is highly recommended to involve test engineers in design reviews in order to ensure a comprehensive test strategy.
GOEPEL offers Design for Testability guidelines and even offers DFT analysis for Boundary Scan free of charge. Simply contact us to request further information.
BSDL Verification
The IEEE 1149.1 standard requires that vendors of Boundary Scan
compliant devices provide so called BSDL files. BSDL (Boundary Scan
Description Language) files provide details about the test resources
implemented in such a device and are used by practically all Boundary
Scan tools. Even though most BSDL files are correct these days, there
is always a chance of a syntax error or, worse, an description error
(for example a definition of less Boundary Scan cells than physically
implemented in the chip, wrong instruction op-codes, or a wrong order
of Boundary Scan cells). The execution of Boundary Scan tests that have
been generated based on incorrect BSDL files will result in false
diagnostics or, in the worst case, has potential to cause damage on the
Unit Under Test.
GOEPEL offers BSDL
verification tools as well as physical BSDL
verification service. Simply contact
us to
request further information.
Seminars and Training
Boundary Scan technology is continuously evolving. The IEEE 1149.1 standard provides the definition on how to implement respective test resoruces for digital I/O pins in compliant devices. Newer standards, such as IEEE 1149.4 and IEEE 1149.6 define test resources for analog and mixed signal pins and for high speed I/O pins, respectively. An Unit Under Test will always implement some non-Boundary Scan circuitry, though (devices that do not implement any of these test resources), such as simple buffers, memory devices, or glue logic and interface circuits, just to name a few. Another application of Boundary Scan is the on-board and in-system programming of programmable devices such as FLASH EEPROM, serial EEPROM, PLD and FPGA devices. GOEPEL's SYSTEM CASCON Boundary Scan software suite provides all the tools needed to develop test and programming applications for such devices.
GOEPEL offers a variety of seminars and training programs covering Boundary Scan technology and GOEPEL Boundary Scan tools. Seminars are offered as half day and full day events, training classes last from one day to four days, depending on the curriculum. Both, seminars and training classes can be customized to cover specific topics and can be provided on-site for a corporate audience. We also offer web based tarining (e-Learning) through so called Webinars and conference calls. Simply contact us to request further information or to schedule an event.
Boundary Scan Coach
This interactive learning software provides answers to questions such as:
- How to stimulate and observe board and system level interconnects with JTAG/Boundary Scan?
- How does the Test Access Port (TAP) work?
- How does the serial transmission of Boundary Scan test pattern work?
The Boundary Scan Coach illustrates hwo Boundary Scan resources can be accessed and how they can be utilized for structural interconnect testing. The tool allows the application of test vectors to a Unit Under test - virtually or on a real board - to demonstrate the IEEE 1149.1 principle. Please contact us to request further information.
