GOEPEL can provide Design for Testability guidelines and offers DFT analysis for JTAG / boundary scan and Embedded System Access (ESA) applications free of charge.
As is the case with any test methodologies, board and system test based on JTAG / boundary scan requires some Design for Testability (DFT). For example, all devices featuring a JTAG compliant Test Access Port (TAP) should be linked up in one or more scan chains that are accessible, ideally through a connector. Under certain circumstances it may be desirable to configure the Unit Under Test with multiple scan chains, in other cases just one chain may be beneficial.
Certain types of boundary-scan test applications demand their own set of DFT rules. The point is, the board/system designer is in charge of making the Unit Under Test boundary-scan testable. It is highly recommended to involve test engineers in design reviews in order to ensure a comprehensive test strategy can be implemented.
DFT Analysis steps includes:
- Analyze scan chain design
- Obtain and analyze BSDL files
- Analyze testability of non-boundary scan circuitry on the unit under test and
- Recommend improvements of test coverage to take full advantage of embedded system access resources