Training & Seminars

Boundary Scan technology is continuously evolving. The IEEE 1149.1 standard provides the specification for respective test resources on digital I/O pins in compliant devices. Newer standards, such as IEEE 1149.4 and IEEE 1149.6 define test resources for analog and mixed signal pins and for high speed I/O pins, respectively. And a number of standardization efforts related to JTAG / Boundary Scan have recently been completed (e.g. IEEE 1149.7, IEEE 1149.8.1, IEEE 1500, IEEE 1581) or are under way (e.g. IEEE P1838, IEEE P1687, SJTAG).

An Unit Under Test will always include some non-Boundary Scan circuitry, though (devices that do not implement any of these test resources), such as simple buffers, memory devices, or glue logic and interface circuits, just to name a few. Another application of Boundary Scan is the on-board and in-system programming of programmable devices such as Flash EEPROM, serial EEPROM, PLD and FPGA devices. In recent years, the utilization of on-chip emulation resources for board and system level test applications has become popular, too. GOEPEL's SYSTEM CASCON Boundary Scan software suite provides all the tools needed to develop any such test and programming applications.


GOEPEL offers a variety of seminars and training programs covering Boundary Scan technology and GOEPEL Boundary Scan tools. Seminars are offered as half day and full day events, training classes last from one day to four days, depending on the curriculum. Both, seminars and training classes can be customized to cover specific topics and can be provided on-site for a corporate audience. We also offer web based training (e-Learning) through Webinars and conference calls.

GOEPEL Solutions for Training & Seminars

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