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Structural manufacturing test

When we talk about "structural manufacturing test", we are referring to tests applied to electronics during the manufacturing process in order to identify structural defects on the unit under test, such as open (not properly connected) device pins, shorted circuit nodes (solder bridges), missing components, and more.

JTAG / boundary scan

JTAG / boundary scan test resources, as defined in IEEE Std 1149.1 and related standards, help us to regain test access on today's complex, high-density printed circuit board assemblies. Ball grid array (BGA) packages and multi-layer PCBs with internal-only signal traces, for example, drastically limit the test access that can be achieved with physical probe access (e.g. with bed-of-nail based or flying probe based in-circuit test). Boundary scan cells embedded in integrated circuits can be utilized as test access points for connectivity tests and even for the verification of circuit functions.

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SYSTEM CASCON

The JTAG / boundary scan software environment SYSTEM CASCON provides powerful tools for device, board, and system level test, debug, and in-system programming applications. Upon import of design data (device models and netlist information), one can develop JTAG application such as structural connectivity tests suitable for use throughout the entire product life cycle, starting with prototype verification.

Learn more about SYSTEM CASCON or contact us to arrange a demo.