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System Test

One of the major advantages of JTAG / boundary scan is that it simplifies system level interconnect test dramatically. Using this technology, connections between boards plugged into a backplane or between motherboard and daughter-cards can be verified easily.
system scan configuration System level test often requires scan chain reconfiguration, though. Especially for backplane test with a multi-drop scan chain configuration, test vectors have to be loaded into or read from the boards involved in the test one at a time. Thus, the scan chains on these boards need to be addressable. System level boundary-scan test application may require a star configuration of multiple scan chains (one or more scan chains on each board connected in parallel to the boundary scan controller). Flexible system level scan chain configurations can be realized with off-the-shelve addressable scan router devices or with IP (Intellectual Property) cores implemented into ASIC or CPLD devices. An example for a system level scan chain configuration is given in the figure on the right.

GOEPEL Electronics supports system level JTAG / boundary scan with its SYSTEM CASCON tool suite, which includes powerful tools for automated test generation of system connectivity test and in-system programming applications.

Contact us to learn more about system level test in general and about tools and services offered by GOEPEL Electronics in particular.

SJTAG

The goal of the SJTAG (System JTAG) working group is to define the data contents and formats communicated between external test manager platforms and system-internal embedded test controllers (ETC), and between ETCs and the unit under tests (UUTs, system elements) they serve, in an open-standard, vendor-independent and non-proprietary way. SJTAG is working under the IEEE umbrella.