Introduction to JTAG / boundary scan related technologies

To eliminate manufacturing faults, their sources have to be revealed. In order to achieve this, the stimulation and evaluation of the circuit nodes has proven to be effective. Manufacturers of integrated circuits pioneered the development of "scan procedures". Well known is LSSD (Level Sensitive Scan Design) which was introduced by IBM in the 1960s. The basic idea is the division of digital circuits into combinatorial and sequential (typically flip-flops) circuit parts. The functional flip-flops are extended so that they can be used as shift registers in test mode. Test vectors can now be loaded into these shift registers and thus the flip-flops become access points to circuit nodes that can be stimulated and observed. The test of the combinatorial circuit parts can be executed through these circuit nodes, which are tested implicitly at the same time.

As sequential logic is part of many integrated circuits, the test of peripheral circuitry had to be executed using external test resources rather than the shift registers mentioned above - until Boundary Scan was invented. It picks up the principle of flip-flops being connected to a shift register, yet this register is implemented into the silicon at the boundary of the circuit for the sole purpose of test access. For these flip-flops (Boundary Scan Cells) would impair the normal functioning of the circuit, they are connected to or disconnected from device pins and functional core via multiplexers. The basic functions of this architecture are:

to capture test result vectors into the Boundary Scan cells,
to serially shift in new test vectors and simultaneously shift out test result vectors that were captured,
to apply a test vector previously shifted in to the circuitry to be tested,
Test/stimulation of the inside of the integrated circuit (internal test), and
Test/stimulation of outside signals being connected to the integrated circuit (external test).

An integrated circuit featuring this Boundary Scan capability has to be told which actions to carry out and it has to be synchronized with other Boundary Scan capable devices on the Unit Under Test (UUT). Thus, beside the actual test vectors it has to be provided with test instructions. For the purpose of providing the test instructions as well as test vectors and for synchronization between Boundary Scan capable components (short: BScan components) a test interface is required.

In order to define such an interface and to standardize the Boundary Scan circuitry, a group of more than 200 members consisting of the leading manufacturers of integrated circuits, suppliers of test systems and manufacturers of electronic products came together to form the Joint European Test Action Group, later the Joint Test Action Group (JTAG). This group defined a four-wire test bus which optionally may be supplemented with a fifth test reset line. In order to make this test bus interface and the Boundary Scan test methodology a success as a platform which is independent from the manufacturer, it was proposed to the IEEE for standardization and eventually was approved as IEEE 1149.1 standard in 1990. Several extensions have been made since, and the working group is currently working on a new revision of IEEE Std 1149.1, scheduled for late 2011 or early 2012.

There has been work to complement the testability achieved by IEEE Std 1149.1. One working group developed an analog test bus interface for mixed signal test applications – standardized as IEEE 1149.4, approved in 1999. Another working group developed a multi drop test bus interface for test on system level, known as 1149.5 (although, this standard has not been adopted widely in the industry). The latest developments in high speed interconnects on board and system level initialized work on a test methodology for AC coupled and differential interconnects based on the 1149.1 test bus protocol. Work began in May 2001, was finalized in late 2002, with standardization as IEEE 1149.6 in January 2003. Newer IEEE standards related to IEEE 1149.1 include IEEE 1149.7 and IEEE 1581. And there are ongoing efforts today, extending the principles of IEEE 1149.1 to new applications and capabilities (e.g. IEEE P1838, IEEE P1149.8.1, IEEE P1687, SJTAG).

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