JTAG / Boundary Scan technology

Boundary Scan test based on IEEE 1149.1 is well established today. However, in recent years new challanges have arrived the limit the test coverage achievable with traditional Boundary Scan testing. In order to provide solutions to test problems related with analog and mixed signal circuitry, differential signaling, and AC coupled networks new standards have been developed as part of the IEEE 1149.x family of test standards (IEEE 1149.4 and IEEE 1149.6, respecttively). Still new developments are under way to standardize the test of static interconnects (IEEE P1581), the access to device internal instrumentation, such as emulation, debug, and other instruments embedded in chips (IEEE P1687), and the definition of a compact JTAG interface (IEEE P1149.7).

The following IEEE working group websites provide details regarding standardization efforts:

IEEE 1149.1
IEEE 1149.4
IEEE 1149.6
IEEE 1532
IEEE 1500
IEEE P1149.7
IEEE P1581
IEEE P1687

Feel free to contact us for details regarding any of those standards and initiatives.
IEEE standards can be downloaded here:

IEEE 1149.1

The effort to develop a standardized test method that can solve test access problems caused by ever denser printed circuit designs, shrinking device geometries and new device packaging (such as BGA and CSP) started in the mid 1980s, when a group of European companies and institutions formed the Joint European Test Action Group (JETAG), which later changed its name to Joint Test Action Group (JTAG) when North American organizations joined the group. Working hard on creating the first standardized test access technology, the group approached IEEE in the late 1980s to sponsor the effort. In 1990, the JTAG / Boundary Scan architecture was published as IEEE 1149.1 (Standard Test Access Port and Boundary Scan Architecture [1]). Since then, various improvements have been made to the original standard; the latest revision has been approved and published in 2001. The JTAG / Boundary Scan technology owes its success to its elegant way of providing test and debug access to nodes on a printed circuit board (PCB). Even though the IEEE 1149.1 standard is limited to digital circuitry, the test access achievable on today’s designs implementing this technology allows a wide variety of test and debug applications and even supports some tasks not foreseen at the time the standard was developed. Most modern board and system designs make use of Central Processing Units (CPU’s) or Micro Processors (μP’s), Digital Signal Processors (DSP’s), Programmable Logic Devices (PLD’s), and/or Field Programmable Gate Arrays (FPGA’s) – all of which are of digital nature and most of which implement JTAG / Boundary Scan capabilities as defined in IEEE 1149.1.

BSDL

The Boundary Scan Description Language (BSDL), as defined in IEEE 1149.1, Annex B, is used to document the Boundary Scan resources available in a particular IC and to present that information to software tools in a machine readable form for automated processing. Practically all Boundary Scan tools read and analyze BSDL files in order to undertand which test modes are supported by the device and which Boundary Scan cell must be used to toggle a particular pin, for example. More sophisticated tools use BSDL files in conjunction with CAD data (e.g. the netlist of the Unit Under Test) for automated test generation.

IEEE 1149.4

Analog or Mixed signal circuitry is left out by IEEE 1149.1. Recognizing this shortcoming, an IEEE working group was formed in the early 1990s with the purpose to develop a standardized test access methodology for analog and mixed signal pins. In 1999 the effort resulted in the approval of the IEEE Std. 1149.4 (Standard for a Mixed Signal Test Bus). The purpose of this standard is to provide the means to measure and characterize device level or board level mixed-signal and analogue parameters. IEEE 1149.4 compliant devices (which are also 1149.1 compliant) feature two additional test bus signals (AT1 and AT2). These two test bus signals can be connected to I/O pins through a switching structure (TBIC and ABM) for the purpose of test. Typically, they are used to provide a constant current to one pin and to measure the voltage on that and another pin (one by one). This test approach is used to measure resistance and capacities in the circuitry.

IEEE 1149.6

Another shortcoming of IEEE 1149.1 lies in its quasi static test patterns. When looked at sequentially, test patterns are applied at a fairly low rate, due to the fact that every pattern has to be loaded and unloaded serially through the Boundary Scan chain. The serial access method of IEEE 1149.1 practically eliminates any possibility to apply test pattern on dynamic I/O pins at functional speed (each test pattern requires hundreds or thousands of TCK clocks to be shifted through the scan chain). With the arrival of AC coupled networks, Boundary Scan hit a road block. Serial capacitors in a signal path hinder the transmission of static test pattern as applied with IEEE 1149.1 compliant test resources. To solve this problem and to allow Boundary Scan tests to include such AC coupled networks, another IEEE working group defined the IEEE Std. 1149.6, approved in 2003. This Standard for Boundary Scan Testing of Advanced Digital networks is based on the transmission of signal transitions, rather than static logic High and logic Low levels.

IEEE 1500

This Standard for Embedded Core Test has been created to address the test complexity of System on Chips (SoCs) by providing a standardized test bus interface and a set of rules applied to isolate a particular core from the logic surrounding that core. The purpose of this isolation boundary (called a wrapper) is to allow the test of a core without any influence from circuitry outside the core, while keeping the amount of signals that must be brough out to the SoC level to a minimum. Similar to the Boundary Scan Register in a JTAG/Boundary Scan compliant device, the wrapper in a IEEE 1500 compliant devices comprises of wrapper cells for each functional I/O port. The wrapper cells are stringed together to form one or more wrapper scan chain(s). The wrapper cells are used to observe and stimulate the core logic they are linked to.

IEEE 1532

In-System Programming of PLD and FPGA is another application that utilizes the TAP defined in IEEE 1149.1. For years, different vendors of programmable devices had proprietary programming algorithms implemented in their device. Sometimes this caused problems when devices from different vendors where mixed within the same scan chain. With IEEE 1532 the programming algorithms for compliant devices as well as the format of programming data has been standardized for the first time. Thus, several devices (compliant with this standard) from different vendors within the same chain are now programmed using the same algorithms, simplifying programming tools and logistics. Furthermore, IEEE 1532-2002 defines the optional implementation of concurrent programming features. Concurrent programming can provide a significant improvement in programming time as more than one device can be programmed at the same time, rather than sequentially.

Other test related standards and standardization efforts

JTAG/Boundary Scan has been very successful in the past years and is widely adopted throughout the electroncis incustry. The test access port defined in IEEE 1149.1 enables device, board, and system level test applications, debug and emulation access, and ven in-system programming. Still there is room for improvement in some areas, such as cluster testing, access to embedded instruments from various IP vendors, test of multi core devices and system-on-chip, and so on. In the following we list several initiatives for the standardization of test technologies as well as a few related industry standards.

IEEE P1581

Today, IEEE 1149.1 test resources are implemented in many digital circuits (such as CPU’s, DSP’s, PLD/FPGA’s, interface devices, etc.). Even some memory components (e.g. some SRAM and FIFO components) have Boundary Scan implemented, although some of them do not support the EXTEST capability as defined in IEEE 1149.1. However, many Memory components do not have any test resources built in. The connectivity between Boundary Scan compliant components and such memory devices can only be tested by means of cluster testing (writing to the memory and reading back pattern written to the memory). This requires full access to the memory control pins, though. Many

SDRAM or newer synchronous memory architectures are implemented on board level with clock circuitry that cannot be synchronized with Boundary Scan. That means that these memory structures cannot be tested via Boundary Scan in cluster tests. Today, no standard test methodology for memory testing is available. One approach introduced in the late 1990’s was SCITT. An IEEE working group (P1581) has been formed to create a standard test methodology for memory interconnect testing. In principle, P1581 describes test circuitry to be implemented in a memory device that bypasses the memory block itself and instead provides a logic connection between input and output pins (using simple logic gates). By stimulating the memory input pins and observing its output pins via BScan devices connected to the memory, board level connectivity can be verified; simplifying and accelerating this kind of test dramatically.

IEEE P1687

Also referred to as IJTAG (Internal JTAG), the IEEE P1687 working group intends to develop a methodology for access to embedded test and

debug features (but not the features themselves) via the IEEE 1149.1 Test Access Port (TAP) and additional signals that may be required. The IEEE 1149.1 standard specifies circuits to be embedded within a Integrated Circuit to support board test, namely the Test Access Port (TAP), TAP Controller, and a number of internal registers. In practice, the TAP and TAP controller are being used for other functions well beyond boundary scan in an ad-hoc manner across the industry to access a wide variety of internal chip test and debug features. The purpose of the IJTAG initiative is to provide an extension to the IEEE 1149.1 standard specifically aimed at using the TAP to manage the configuration, operation and collection of data from embedded test and debug circuitry. There exists the widespread use of embedded instrumentation (such as BIST Engines, Complex I/O Characterization and Calibration, Embedded Timing Instrumentation, etc.) each of which is accessed and managed by a variety of external instrumentation using a variety of mechanisms and protocols. Therefore, there exists a need for a standardization of these protocols in order to ensure an efficient and orderly methodology for the preparation of tests and the access and control of these embedded instruments.The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features.
(excerpt from the IEEE P1687 PAR application)

IEEE P1149.7

The Mobile Industry Processor Interface (MIPI) Test and Debug Working group has selected a new test and debug interface, called Compact JTAG (cJTAG), which builds upon the IEEE1149.1 standard. The goal of cJTAG, proposed as IEEE standard P1149.7, is to enable advancements in test and debug functionality while maintaining compatibility with IEEE 1149.1 by creating a superset of the IEEE 1149.1 test interface. A primary objective of cJTAG was to preserve the industry’s hardware and software investments in this standard. With cJTAG, existing tools or Debug and Test Systems (DTS), such as an IEEE 1149.1 emulator, and Target System (TS) chips, can simply be extended with adapters to convert to the cJTAG interface.

SJTAG

The system-level JTAG initiative, called System JTAG (SJTAG), was created in 2005 with the mission to tackle problems associated with the extended test and configuration of IEEE 1149.1 infrastructure within complex multi-board systems. A White paper on SJTAG, authored by members of the initiative, is available for download here. This software based initiative focuses on the development of a standardized test vector format and protocol for remote communication with a Unit Under Test and on the optimization of the reuseability of vectors between tester platforms and of the transfer to and execution of test vectors on remote systems, assuming a remote, on-board boundary scan controller.

PXI

Managed by the PXI System Alliance, with more than 65 members, PXI (PCI eXtension for Instrumentation) has been developed and introduced by National Instruments in 1997/98. PXI is based on the Compact PCI (cPCI) specification, defined in the mid 1990s. Both feature the same electrical characteristics as PCI, with a throughput of 132 Mbyte/sec (up to 256Mbyte/sec at 66MHz). Using the same form factor as cPCI – the Eurocard format (IEC-297, IEEE1101.1, IEEE1101.10) – PXI adds system-level specs for synchronization and timing, cooling, environmental and EMI (Electromagnetic Interference) testing, software framework and device driver (for automatic device recognition). The PXI interface uses 2mm pitch high-density, impedance-matched backplane connectors (IEC-1076).
Features specifically implemented in PXI to support test applications include:

a System reference clock (10MHz TTL common reference clock for synchronization available on each slot with <1ns skew);
8 TTL trigger bus lines (for trigger, hand-shake, clock signals to be shared between modules);
a Star Trigger bus (independent trigger line for each slot originating on Star Trigger slot, matched propagation delay <1ns); and
a Local Bus (daisy-chained, 13 signals connecting each slot to its adjacent slot to the left and right, for analog signals up to 42V).

LXI

LXI (LAN eXtension for Instrumentation) is a new industry standard, created for rack and stack based test equipment communicating over Local Area Network (LAN) following the Ethernet protocol (IEEE Std.802.3). LXI can be viewed as successor for the aging GPIB industry standard, solving many problems related to latter technology’s performance limitations and cost. The LAN eXtensions for Instrumentation (LXI)

specification, released in version 1.0 in September 2005, has been created and is managed by the LXI Consortium, which includes more than 50 member companies. First products have been introduced in December 2005.

Being a natural successor of GPIB, LXI is a standardized platform for “rack and stack” type or stand-alone, benchtop instruments. LXI does not compete with PXI or VXI, which define modular, plug-in card cage based instrumentation platforms, but rather complements these standards. Some applications can be satisfied with one or the other approach, while others demand the integration of various test platforms in hybrid systems. LXI is well suited for remote, distributed, and highly dispersed test and measurement applications, for example.

LXI is more flexible than modular instruments in regard to mechanical features (physical dimensions needed to fit required circuitry and interface elements, for example) and instrument internal requirements such as power consumption and cooling. Vendors can develop instruments with unique electrical and physical requirements, but with standardized interface control (LAN, WLAN). Since LXI is not backplane based, there is no significant system overhead cost other than network infrastructure (cabling, routers, etc.); however, every LXI device requires its own power supply and instrument control circuitry. As defined in the LXI standard, each compliant instrument provides the means for remote access from a web browser anywhere within the network through a web server embedded into the device.

STAPL (JESD 71)

The Standard Test And Programming Language is primarily used for device programming (for PLD and FPGA devices) through a IEEE 1149.1 compliant Test Access Port. However, there are some tools that utilize the language for test applications. STAPL provides improvements over SVF (such as conditional branching and looping, etc). STAPL is also looked at by various initiatives (such as IEEE P1687 and SJTAG) in regard to its feasability for other purposes.

SVF

Serial Vector Format has been around for a long time. This industry standard is in use for both test and ISP applications. SVF has its limitations, though, in that it does not support conditional looping and branching, for example.

Industry links

IEEE	Institute of Electrical and Electronics Engineers, Inc
BTTAC	TTTC Board Test Technical Activities Committee; successor to the Board Test Action Group (BTAG)
ATE World	Online community for Automatic Test Equipment professionals
Best Test	A.T.E. Solutions, Inc.; independent test engineering consulting and educational firm
Evaluation Engineering	Industry magazine, Nelson Publishing
PXI Test & Technology	Industry magazine, OpenSystems Publishing
Test & Measurement World	Industry magazine, Reed Electronics